Jacek M. Zurada, Ph.DDistinguished University Scholar, IEEE Fellow | |
| Computational Intelligence Laboratory Electrical and Computer Engineering 405 Lutz Hall University of Louisville Louisville, KY 40292 | phone: (+1 502) 852 6314 fax: (+1 502) 852 3940 email: jacek.zurada .a_t. louisville.edu www: ci.louisville.edu/zurada |
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ECE 515 - Introduction to VLSI Systems
Please refer to the Blackboard for updates and the official information.
The purpose of this course is to teach the students a standard methodology of structured digital VLSI circuit design in CMOS technology and develop VLSI design experience.
Prerequisites: ECE/CECS 210, co-requisite ECE/CECS 510 (or equivalent courses) (ECE 615, CECS 525 or consent of the instructor may be substituted as a co-requisite).
| TOPIC | WEEKS | COMMENTS |
|---|---|---|
| 0. Introduction to Unix, SPICE, and Magic | 1 | ST Fife VLSI Lab, WSS 221 |
| 1. Introduction: stick diagrams/gate arrays, MOS transistors, NMOS/CMOS inverters, transfer characteristics, noise margins, optimisation of VTC, timing considerations, NANDs and NORs. | 3 | Project 1 starts about here |
| 2. Fabrication and Standard Design Rules: photolithography process, VLSI MOS transistor fabrication scheme, lambda design rules, layout design project. | 0.5 | Educational movie on CMOS VLSI Fabrication Process |
| 3. Electrical parameters and scaling effects. | 0.5 | Project 2 starts about here |
| 4. Combinational VLSI Logic: logic realizations, NOR synthesis, compound gates, structured gate arrays, PLAs use as standardization tool, pass transistor arrays, transmission gates. | 3 | Chip project initiated and approved |
| 5. Register Arrays and Stack Design: clock control, static and dynamic memory cells, flip-flops, registers, LIFO arrays. | 1.5 | Project 3 starts about here |
| 6. Finite State Machines: fundamentals, PLA-based implementation. | 1 | Final chip design outlined |
| 7. Design of Standard VLSI Functional Blocks and Subsystems: counters, adders, ROM, and RAM cells, ALUs, etc. | 2.5 | Project 4 about here Final chip design progresses |
| 8. Overview of Semi-Custom Techniques. | 0.5 | Final chip design ready, Rept. due |
| 9. Tests | 1.5 | 3 tests every 4-5 weeks each |
This course involves comprehensive computer-aided layout design and subsystem simulation experience using Berkeley VLSI Design Tools under Unix. Standard VLSI CAD Tools used include Magic, SPICE, and Irsim. Lab team of 2-3 students are required to complete a chip project and generate fabrication files. Finished projects are submitted for fabrication to MOSIS and need to be tested about 3 months therafter.
Textbooks
ECE 515: J. M. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits; A Design Perspective, 2nd Ed., Pearson Education, Inc., 2003
ECE 514: A. Broadhead, P. A. Habas, M. K. Muezzinoglu, G. M. Boratyn, and J. M. Zurada, ECE 514 Project Handbook, ECE Dept., UofL, 2006.
Other manuals used are VLSI Design Tools Manuals on display in WSS221
Grading
ECE 515: 60% three quizzes, 15% homework, 15% projects 1-4, 10% final project
ECE 514: 100% projects 1- 4 and final project
Supplemental material
Introduction to Unix · Printing MAGIC design with XV · Introduction to MAGIC · Introduction to SPICE · SPICE models for Project 2 · SPICE to SIM converter
The course may be taken as an EE Elective, EE Program Elective or M.S.E.E. course. Graduate (600-level) Requirement include submitting the Final Project Report which, in addition to discussion of design and verification, also contains one of the following: (i) comparison of selected design with other design found in the technical literature, and (ii) evaluation of speed and efficiency as supported by simulation or analysis.
